1. Field of the Invention
The present invention relates to a method of biasing a nonvolatile flash-EEPROM memory array for reading and writing memory cells.
2. Discussion of the Related Art
Flash-EEPROM memories are known to consist of an array including a number of cells arranged in rows and columns and connected to circuitry enabling them to be written (programmed), read and erased electrically, extremely rapidly, and with high density integration.
Flash-EEPROM memory cells are similar to those of EEPROMs, except that they present a very thin gate oxide layer (between the substrate and floating gate region).
Though highly promising at present, due to the above characteristics--electric erasability and high density--flash-EEPROM memories continue to present several drawbacks limiting their use.
One of the main drawbacks of this type of memory is dispersion of the threshold value of the erased cells (i.e. the voltage to be applied between the control gate and source regions for turning the cell on). Such dispersion, representable by a bell-shaped curve centered about a mean value, is due to the erase process employed, which consists in applying a high voltage to the source regions of the cells for extracting electrons from the floating gate (unlike EEPROM memories wherein erasure is effected by ultraviolet radiation). The outcome of electrically erasing the cells as described above depends on various factors: channel length (which may vary from one cell to another due to misalignment of fabrication masks or other technical problems); the erase voltage applied to each cell (the source regions of flash-EEPROM cells are formed in a single diffusion, which is connected by contacts and at regular intervals to a metal source line; due to the series resistance of the N.sup.+ type diffusion, however, the erase voltage of the cells furthest from the contacts differs from and is lower than that of the closer cells); threshold voltage reached after programming (also variable); and weak erasure phenomena.
Another drawback typical of flash-EEPROM memories is the possibility of read errors, due to the presence of overerased cells and the absence of selection transistors for each cell as on EEPROM memories.
It is an object of the present invention to provide a flash-EEPROM memory biasing method designed to overcome the aforementioned drawbacks.